SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 1 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 6.5 m ? , bidirectional battery switch in compact wcsp description the SIP32104 bidirectional swit ch feature reverse blocking capability to isolat e the battery from the system. the internal switch has an ultra low 6.5 m ? (typ. at 3.3 v) on-resistance and operates from a +2.3 v to +5.5 v input voltage range, making the devices ideal batt ery-disconnect switches for high capacity battery applications. the SIP32104 has slew rate control, making it ideal in large load capacitor as well as high current load switching applications. the device is also highly efficient, consuming only 110 na (typ.) current in shutdown and while operating. the SIP32104 has an active low enable. it can interface directly with a low voltage control signal. the SIP32104 is available in an ultra compact 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch wcsp package with top side lamination. the device operates over the temperature of -40 c to +85 c. features ? bidirectional on and off ? 7 a continuous current capability ? ultra-low r on , 6.5 m ? (typ.) at 3.3 v ? wide input voltage, 2.3 v to 5.5 v ? slew rate controlled turn on ? low quiescent current: 110 na ? compact 12-bump, 1.3 mm x 1.7 mm x 0.55 mm wcsp package ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? smartphones and tablets ? digital still / video cameras ? portable meters an d test instruments ? communication devices with embedded batteries ? portable medical an d healthcare systems ? data storage ? battery bank typical application circuit fig. 1 - typical application circuit note ? ge1 denotes halogen-fr ee and rohs-compliant marking ordering information part number marking enable enable pull resistor package temperature SIP32104db-t1-ge1 32104a low no pull 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch wcsp package -40 c to +85 c SIP32104evb - - - evaluation board - port a port b to battery pack s y s tem power input charger output s y s tem charging block charging control and regulator s y s tem connector power input s lew rate gate drive logic level s hift g nd en 1234 a b c fywl 3 2104a
SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 2 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. negative current injection up to 300 ma b. all bumps soldered to 1" x 1", 2 oz. copper, 4 layers pc board c. derate 13.7 mw/c above t a = 70 c ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating/conditions for extended peri ods may affect de vice reliability. notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum b. typical values are for design aid only, not guaranteed nor subject to production testing c. for v in outside this rang e consult typical en , en threshold curve absolute maximum ratings parameter conditions limit unit v pa , v pb reference to gnd -0.3 to +6 v pulse at 1 ms re ference to gnd a -1.6 v en reference to gnd -0.3 to +6 maximum continuous switch current 7 a maximum pulse current 100 s pulse 15 esd (hbm) 8000 v operating temperature -40 to +85 c operating junction temperature 125 storage temperature -65 to +150 thermal resistance ( ? ja ) b 73 c/w power dissi pation (p d ) b, c t a = 70 c 1096 mw specifications parameter symbol test conditions unless specified limits unit v in = v pa /v pb = 2.3 v to 5.5 v, t a = -40 c to +85 c (typical values are at v pa , v pb = 4.2 v, c pa , c pb = 0.1 f, t a = 25 c) min. a typ. b max. a power supply operating voltage c v pa/pb 2.3 - 5.5 v quiescent current i q v en = 0 v, no load - 110 400 na shutdown current i shdn v en = v in , no load - 110 400 na internal fet on-resistance r ds(on) v pa /v pb = 2.3 v, i l = 500 ma, t a = 25 c - 8 13 m ? v pa /v pb = 3.3 v, i l = 500 ma, t a = 25 c - 6.5 10 control en input logic-low voltage c v il --0.4 v en input logic-high voltage c v ih 1.4 - - en input logic hysteresis v i(hys) - > 200 - mv timing output turn-on delay time t d(on) v in = 4.2 v, r l = 100 ? , c l = 0.1 f, t a = 25 c -0.8- ms output turn-on rise time t r -1- output turn-off delay time t d(off) -0.12- output turn-off fall time t f -0.1-
SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 3 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 bump configuration fig. 2 - wcsp12, 1.3 mm x 1.7 mm functional block diagram typical characteristics (internally regulated 25 c, unless otherwise noted) fig. 3 - quiescent vs. input voltage fig. 4 - shutdown current vs. input voltage bump description bump number name function a1, b1, a3, b3, c3 pb power port b c1 gnd ground a2, b2, c2, b4, c4 pa power port a a4 en switch enable input, active low top view ( s older bump s on bottom) a1 1234 a c b port a port b /en port b port a port a port b port b port a port a port b g nd a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 gnd en, SIP32104 port b port a internal bia s circuit s lew rate gate drive logic level s hift 100 110 120 130 140 150 160 170 180 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i q pa/pb - q uie s cent current (na) v pa/pb (v) 100 110 120 130 140 150 160 170 180 190 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i s hdn-pa/pb - s hutdown current (na) v pa/pb (v)
SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 4 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (internally regulated 25 c, unless otherwise noted) fig. 5 - quiescent vs. temperature fig. 6 - on resist ance vs. temperature fig. 7 - shutdown current vs.temperature fig. 8 - on resistance vs. input voltage fig. 9 - normalized on resistance vs. load current fig. 10 - reverse blocking current (i rb ) vs. output voltage 80 90 100 110 120 130 140 150 - 40 - 15 10 35 60 85 i q pa/pb - q uie s cent current (na) temperature ( c) v pa/pb = 5.0 v v pa/pb = 2.7 v v pa/pb = 4.2 v 2 3 4 5 6 7 8 9 10 -40 -15 10 35 60 85 r d s - on-re s i s tance (m) temperature ( c) i l = 0.5 a v pa /v pb = 4.2 v 80 100 120 140 160 180 -40 -15 10 35 60 85 i s hdn - pa/pb - s hutdown current (na) temperature ( c) v pa/pb = 2.7 v v pa/pb = 5.0 v v pa/pb = 4.2 v 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4. 0 4.5 5.0 5.5 6.0 r d s - on-re s i s tance (m) v pa /v pb (v) i l = 0.5 a 0.95 1.0 1.05 1.1 1.15 1234567 r d s (norm) - normalized on - re s i s tance i out (a) t a = 25 c v pa /v pb = 2.7 v v pa /v pb = 3.3 v v pa /v pb = 4.35 v v pa /v pb = 5 v -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2.02.53.03.54.04.55.05.5 i pb/pa - input current (na) v pa/pb (v) v pb/pa = 2.3 v
SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 5 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (internally regulated 25 c, unless otherwise noted) fig. 11 - rise time vs. temperature fig. 12 - en threshold voltage vs. input voltage fig. 13 - turn-on delay time vs. temperature fig. 14 - turn-off delay time vs. temperature fig. 15 - fall time vs. temperature 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 -40 -15 10 35 60 85 t r -ri s e time (m s ) temperature ( c) v pa/pb = 4.2 v c l = 0.1 f r l = 10 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 2.0 3.0 4.0 5.0 6.0 en thre s hold voltage (v) v pa/pb (v) v ih v il 0.5 0.6 0.7 0.8 0.9 1 -40 -15 10 35 60 85 t d(on) - turn-on delay time (m s ) temperature ( c) v pa/pb = 4.2 v c l = 0.1 f 0.100 0.105 0.110 0.115 0.120 0.125 0.130 0.135 0.140 -40 -15 10 35 60 85 t d(off) - turn-off delay time (m s ) temperature ( c) v pa/pb = 4.2 v c l = 0.1 f r l = 10 0.060 0.061 0.062 0.063 0.064 0.065 0.066 0.067 0.068 -40 -15 10 35 60 85 t f -fall time (m s ) temperature ( c) v pa/pb = 4.2 v c l = 0.1 f r l = 10
SIP32104 www.vishay.com vishay siliconix s17-0469-rev. b, 03-apr-17 6 document number: 78609 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed description the SIP32104 bidirectional switch features reverse blocking capability to isolat e the battery from the system. the internal switch has an ultra low 6.5 m ? (typ. at 3.3 v) on-resistance and operates from a +2.3 v to +5.5 v input voltage range, making the device ideal battery-disconnect switch for high capacity battery applications. the parts can handle 7 a continuous current at both directions. the SIP32104 has slew rate control, making it ideal in large load capacitor as well as high current load switching applications. the SIP32104 is available in an ultra compact 12-bump, 1.3 mm x 1.7 mm, 0.4 mm pitch wcsp package with top side lamination. the device operates over the temperature of -40 c to +85 c. reverse current blocking the SIP32104 is a bidirectional switch that prevent current flowing from either port to the other when the device is disabled. en input SIP32104 has an active-low enable pin which can interface with low voltage gpio directly. the switch is on when en is low and off when en is high. the SIP32104 en pin has no pull up or pull down resistor. switch on and off performance the SIP32104 has a slew rate control. this minimizes the inrush current and provides a soft turn on. fig. 16 - port b turn-on time (v pa = 4.2 v, r l = 10 ? , c l = 0.1 f) fig. 17 - port b turn-off time (v pa = 4.2 v, r l = 10 ? , c l = 0.1 f) device pin out device pin out is design ed for ease of layout. fig. 18 - proposed layout ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package / ta pe drawings, part marking, and reliability data, see www.vishay.com/ppg?78609 . /en g nd port a port b current a1 a2 a3 a4 port a port b /en port b b1 b2 b3 b4 port a port a port b port b c1 c2 c3 c4 port a port a port b g nd
package information www.vishay.com vishay siliconix revision: 16-dec-13 1 document number: 62592 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 wcsp12: 12 bumps (3 x 4, 0.4 mm pitch, 208 m bump heig ht, 1.71 mm x 1. 31 mm die size) notes (unless otherwise specified) (1) laser mark on the silicon die back coated with an epoxy film. (2) bumps are sac396. (3) 0.050 max. co-planarity. (4) laminate tape thic kness is 0.022 mm. (5) use millimeters as the primary measurement. millimeters (5) inches dimension min. nom. max. min. nom. max. a 0.515 0.530 0.545 0.0203 0.0209 0.0215 a1 0.183 0.208 0.233 0.0072 0.0082 0.0092 b 0.234 0.260 0.312 0.0092 0.0102 0.0123 e 0.400 0.0157 s 0.235 0.255 0.275 0.0093 0.0100 0.0108 d 1.270 1.310 1.350 0.0500 0.0516 0.0531 e 1.670 1.710 1.750 0.0657 0.0673 0.0689 ecn: s13-2510-rev. b, 16-dec-13 dwg: 6017 e s e s s e s e e b d e fywl abcde index bump a1 a1 b1 c1 a2 a3 a4 b2 b3 b4 c2 c3 c4 top view bottom view a a1 side view note 3 bump note 2 note 4 recommended land pattern (nsmd) e e e a1 e e
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